1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a hierarchical input/output line structure and a method for arranging the same.
2. Description of the Related Art
As the integration degree of a semiconductor memory device increases and the design rule thereof device decreases, a sense amplifier area and a sub-word driver area become smaller and the number of circuits related to the sensing of the sense amplifier area increases. Accordingly, a load sharply increases. Therefore, a structure in which drivers for driving the sense amplifier are dispersed in the respective conjunction areas is employed in order to rapidly drive a heavy load. Also, as the input/output of more data are required in order to satisfy a high data rate in a highly integrated semiconductor memory device, a hierarchical input/output line (which is referred to as a hierarchical IO line) structure, namely, a structure having a local input/output line and a global input/output line is employed in architecture. A switching circuit and circuits related to sensing for forming the hierarchical IO structure should be arranged in the conjunction area between sub-arrays constituted by memory cells in order to make an inner structure of the above memory device.
FIG. 1 shows a conventional core structure in a memory device having the hierarchical IO structure.
Referring to FIG. 1, the conventional core structure of the memory device includes sub-arrays 1a, 1b, 1c and 1d including a plurality of memory cells, sense amplifiers (SA) 2a, 2b, 2c, and 2d for sensing and amplifying the data of the memory cells of the sub-arrays 1a, 1b, 1c, and 1d, sub-word line drivers (SWD) 3a, 3b, 3c, 3d, and 3e for driving the word lines of the memory cells, local input/output lines LIO1 and LIO2 for receiving and transmitting the output signals of the sense amplifiers (SA) 2a, 2b, 2c, and 2d, global input/output lines GIO for receiving and transmitting the signals of the local input/output lines LIO1 and LIO2, and switching portions 4a, 4b, 4c, 4d, 4e, 4f, 4g, and 4h for transmitting the signals of the local input/output lines LIO1 and LIO2 to the global input/output lines GIO in response to predetermined control signals. Conjunction areas 5a, 5b, 5c, and 5d are formed in each intersection area between the sense amplifiers (SA) 2a, 2b, 2c, and 2d and the sub-word line drivers (SWD) 3a, 3b, 3c, 3d, and 3e in the conventional core structure. Also, in the conventional core structure, a P driver PD1 and N drivers ND1 and ND2 for driving the sense amplifiers 2a, 2b, 2c, and 2d are separated and are respectively included in the conjunction 5c and the conjunctions 5b and 5d and a circuit for the hierarchical IO structure is included in the conjunction 5a. Reference numeral LAPG denotes the control signal of the P driver PD1. Reference numeral LANG denotes the control signal of the N drivers ND1 and ND2. Reference numerals PTG and LTG denote separate gate control signals. Reference numeral BL denotes a bit line. Reference numeral BLB denotes a complementary bit line.
In the conventional core structure, the number of the global input/output lines GIO may be restricted, only a specific sub-word driver SWD area may become larger, and a skew difference of about four sub-array blocks is generated between the respective data from the bit line BL which is nearest to the global input/output lines GIO and the bit line BL which is farthest from the global input/output lines GIO since all the global input/output lines GIO are gathered to the sub-word driver (SWD) 3a. Also, since the P driver PD1 and the N drivers ND1 and ND2 for driving the sense amplifiers 2a, 2b, 2c, and 2d are separated in the conventional core structure, delay skew between the operation of a N-type SA and the operation of a P-type SA basically exists, thus worsening a sensing margin in the operation for sensing a low voltage. Also, even though not shown in FIG. 1, since the additional control signals of the switching transistors 4a, to 4h for forming the hierarchical IO structure are necessary, a layout margin is worsened.